1. Field of the Invention
This invention relates to a frequency generator with a phase locked loop with a loop filter, to a method of generating an oscillating output signal, as well as a method and an apparatus for designing a frequency generator.
2. Description of the Related Art
Frequency generators with phase locked loop (PLL) are employed in many areas, for example in a digital wireless communication system, such as Bluetooth. In such a communication system, a frequency generator generates the carrier signal used for modulation in the transmitter or in transmitting and for demodulation in the receiver or in receiving. A frequency band is associated with each communication system. The communication system may utilize all frequencies within this frequency band to transfer data or information from the transmitter to the receiver. The power of signals the transmitter generates outside the associated frequency band is not allowed to exceed a certain limit, in order not to disturb communication systems utilizing neighboring frequency bands. Signal portions outside the associated frequency band are the greater, the greater the phase noise Sφ with which the carrier or the carrier frequency is burdened. For this reason, the phase noise Sφ has to lie below a predetermined limit Sφmax at a certain frequency offset Δfsp from the carrier.
A further requirement for a frequency generator is that, after announcement of a to-be-output or desired output frequency or target frequency, it adjusts the output frequency sufficiently accurately to the target output frequency within an as-short-as-possible settling time. There are still further requirements, which among other things depend on the modulation method used. In an FSK method (FSK=frequency shift keying), for example, direct modulation capability of the output frequency of the frequency generator is advantageous and desired.
FIG. 10 is a schematic circuit diagram showing an example for a frequency generator based on a phase locked loop. A phase/frequency detector PFD 10 includes a reference signal input 12 for receiving a reference signal with a reference frequency fref, a comparison signal input for receiving a comparison signal with a comparison frequency f1, and a control output 16 for outputting an oscillator control signal. The phase/frequency detector then forms the oscillator control signal depending on the difference between the comparison frequency f1 of the comparison signal present at the comparison signal input 14 and the reference frequency fref of the reference signal present at the reference signal input 12.
A loop filter 20 includes an input 22 connected to the control output 16 of the phase/frequency detector 10 and an output 24. The loop filter 20 usually is a low-pass filter, mostly an RC filter. It filters the oscillator control signal received at the input 22 from the phase/frequency detector 10, in order to generate a filtered oscillator control signal, which it outputs at the output 24. An oscillator 30 includes an input 32 connected to the output 24 of the loop filter 20 and an output 34. The oscillator 30 receives the filtered oscillator control signal from the loop filter 20 at its input 32 and generates an output signal with an output frequency fout at its output 34. The oscillator 30 generates the output signal so that the output frequency fout depends on the filtered oscillator control signal.
The oscillator 30, for example, is a voltage-controlled oscillator (VCO). A VCO usually includes a varactor diode, the capacity of which depends on a present direct voltage. The varactor diode forms the capacity in an LC resonant circuit. The filtered oscillator control signal is a voltage signal applied to the varactor diode (in reverse direction). The greater the applied voltage, the greater the space charge zone and the smaller the electric capacitance between the electrodes in the varactor diode. The smaller the capacitance of the varactor diode, the greater the natural frequency or resonance frequency or output frequency fout of the VCO 30.
A frequency divider 40 includes an input 42 connected to the output 34 of the oscillator 30, an output 44 connected to the comparison signal input 14 of the phase/frequency detector 10, and a control input 46. The frequency divider receives the output signal with the output frequency fout from the output 34 of the oscillator 30 at its input 42 and a frequency factor control signal at its control input 46. The frequency factor control signal represents a frequency factor, which is an integer fraction 1/N of 1. The integer N will be referred to as divisor in the following. The frequency divider 40 generates the comparison signal with the comparison frequency f1 from the output signal with the output frequency fout by a frequency division, wherein the comparison frequency f1 is smaller than the output frequency fout by the frequency factor 1/N, f1=fout/N.
The frequency generator illustrated in FIG. 10 further comprises a ΣΔ modulator 50. The ΣΔ modulator 50 includes an input 52, a reference signal input 54, and a control output 56 connected to the control input 46 of the frequency divider 40. The ΣΔ modulator receives, at its input 50, a signal representing a desired frequency factor 1/Nfrac, which does not have to be an integer fraction of 1, as opposed to the frequency factor processed by the frequency divider 40. The ΣΔ modulator receives, at its reference signal input 54, the same reference signal the phase/frequency detector 10 receives at its reference signal input 12. The reference signal serves as clock signal for the ΣΔ modulator.
The desired frequency factor 1/Nfrac or its inverse, the desired divisor Nfrac, are preferably passed to the ΣΔ modulator 50 in form of an input word K with the binary input word width k at its input 52, wherein Nfrac=N0+xK/2k applies. Here, N0 is a natural number and x+1 the number of (integer) moduli made available by the frequency divider 40. The frequency divider 40 divides the output frequency fout by a divisor N, which takes on one of the integer values N0, N0+1, N0+2, . . . , N0+x. If, for example, fref=8 MHz, N0=124, x=2, and k=4 applies, the input word K may take on the values 0, 1, 2, . . . , 15, the divisor N the values N=124, N=125, N=126, and the frequency factor 1/N the values 1/N= 1/124, 1/N= 1/125, and 1/N= 1/126.
If the ΣΔ modulator 50 receives an input word K=0, 1, 2, . . . , 15 at its input 52, it controls the frequency divider 40 so that the divisor N corresponds to the desired divisor Nfrac, i.e. one of the values 124,0,124,125,124,250, 124,375, . . . , 125,750 or 125,875, in temporal average. If the desired divisor Nfrac is integer (K=0, Nfrac=124 and K=8, Nfrac=125), the ΣΔ modulator 50 generates a frequency factor control signal at its control output 56, which causes the corresponding frequency factor ( 1/124 or 1/125) to be adjusted in the frequency divider 40 in constant manner. If the desired divisor Nfrac is not an integer (K=1, Nfrac=124,125 to K=7, Nfrac=124,875 and K=9, Nfrac=125,125 to K=1, Nfrac=125,875), the ΣΔ modulator 50 generates, at its control output 56, a time-variable frequency factor control signal causing the frequency divider 40 to alternatingly set the divisor N to one of the (integer) values 124, 125, 126. The ΣΔ modulator 50 determines the portion the individual frequency factors have of the overall time, so that the temporal average of the frequency factors adjusted by the frequency divider 40 corresponds to the desired frequency factor 1/Nfrac. In other words, the direct component of the frequency factor control signal generated by the ΣΔ modulator 50 ensures that the (mean) output frequency of the output signal is fout=Nfrac fref.
While, without the ΣΔ modulator 50, only the output frequencies fout=992 MHz, 1000 MHz, 1008 MHz would be adjustable by the frequency divider 40, the ΣΔ modulator 50 controls the frequency divider 40 so that, with the numerical example mentioned, 16 different output frequencies at a distance of 1 MHz can be generated, fout=992 MHz (K=0), 993 MHz (K=1), 994 MHz (K=2), . . . , 1007 MHz (K=15).
In the embodiment illustrated, a circuit of two current sources 60, 62 and two switches 64, 66 is connected between the control output 16 of the phase/frequency detector 10 and the input 22 of the loop filter 20. The first current source 60, the first switch 64, the second switch 66 and the second current source 62 are connected in series between a supply potential terminal and ground in this arrangement. The switches 64, 66 are connected to the control output 16 of the phase/frequency detector 10 and are controlled individually and depending on the reference frequency fref and the comparison frequency f1 by the phase/frequency detector 10. They convert the oscillator control signal generated by the phase/frequency detector 10 to a modified oscillator control signal, which is fed to the loop filter 20. Functionally, the arrangement of the current sources 60, 62 and the switches 64, 66 may be regarded as a constituent of the phase/frequency detector.
The phase/frequency detector 10, the loop filter 20, the oscillator, and the frequency divider 40 form a locked loop. The oscillator control signal generated by the phase/frequency detector 10 due to a phase difference between the reference signal and the comparison signal controls the oscillator 30 so that the comparison signal has a constant phase relation to the reference signal.
A further important property of the ΣΔ modulator is that it controls the integer divisors N, N+1, N+2, . . . , N+x (in the concrete numerical example: 124, 125, 126) of the frequency divider 40 in a quasi-random sequence so that the quantization noise of the ΣΔ modulator 50 has an advantageous noise spectrum. The advantageous noise spectrum contains little power at low-noise frequencies and much power at high-noise frequencies. These high-noise frequencies, however, are largely suppressed or removed by the loop filter.
An advantage of the ΣΔ modulator fractional-N frequency generator or frequency generator with the ΣΔ modulator described on the basis of FIG. 10 is that it may be operated at an almost arbitrary reference frequency fref or the reference frequency fref does not restrict the series of possible output frequencies fout or their frequency distance. Its phase noise and its settling time are substantially determined by the transfer function HPLL(s) of the phase locked loop. The ΣΔ fractional-N frequency generator from FIG. 10 can further be modulated easily, for example by means of pre-emphasis methods or two-point modulation.
If the phase locked loop 10, 20, 30, 40 and particularly its loop filter 20 is narrow band, the constant switching of the frequency divider 40 between various frequency factors 1/N or between various divisors N caused by the ΣΔ modulator 50 has a weaker effect on the output frequency fout than if the phase locked loop is broadband. On the other hand, the more broadband it is, the quicker the phase locked loop is capable of following a desired change of the output frequency fout. Phase noise and settling time of the phase locked loop and the frequency generator thus have to be balanced against each other. How difficult it is to find a compromise here, however, depends on the amplification KVCO of the VCO 30, the properties of the phase/frequency detector 10 and of the loop filter 20, among other things.
There is a series of influences on the phase noise of a ΣΔ fractional-N frequency generator. Among those are the phase noise of the free-running oscillator 30, the phase noise of the reference signal, the jitter of the frequency divider 40, the noise of the phase/frequency detector 10 and of the loop filter 20. Usually dominant, however, is the quantization noise Nq of the ΣΔ modulator 50. In their article “A CMOS Monolithic ΣΔ-Controlled Fractional-N Frequency Synthesizer for DCS-1800” (IEEE J. Solid-State Circuits, vol. 37, No. 7, pp. 835–44, 2002), D. de Muer and M. S. J. Steyaert indicate an approximation formula for the contribution of the quantization noise Nq of the ΣΔ modulator to the phase noise Sφ of the ΣΔ fractional-N frequency generator. From this approximation formula, the inequality
                        H        PLL            ⁡              (                  2          ⁢                                          ⁢          π          ⁢                                          ⁢          Δ          ⁢                                          ⁢                      f            sp                          )                  <                              S          ϕmax                ⁡                  (                      Δ            ⁢                                                  ⁢                          f              sp                                )                    ⁢                        3          ⁢                      f            ref                    ⁢                                                                  1                -                                  z                                      -                    1                                                                                      2                                                Δ            2                    ⁢                      π            2                    ⁢                                                                                    H                  q                                ⁡                                  (                  z                  )                                                                    2                              may be derived for the magnitude of the transfer function. If this inequality is satisfied, the phase noise Sφ of the frequency generator at a frequency offset Δfsp from the carrier or a carrier frequency is not greater than the limit Sφmax. Here, HPLL(s) is the transfer function of the phase locked loop, fref the reference frequency, Hq(Z) the noise-forming function of the ΣΔ modulator, z=exp(j2πΔfsp/fref), Δ=x/(2B−1), and B the width of the output word of the ΣΔ modulator.
The settling time of a frequency generator is, according to definition, the time the frequency generator needs after announcement of the frequency to be output, to adjust the output frequency fout accurately up to a relative error α. If the phase difference between the reference signal and the comparison signal remains smaller than 2π during the settling process, the relative frequency error may be calculated by determining the response of the so-called error transfer function He(s)=(1−HPLL(s)) to a jump of the height ΔNfrac/Nfrac (at a time instant t=0). The settling time then corresponds to the earliest time instant after which the magnitude of the relative frequency error remains smaller than α.